1. Field of the Invention
The present invention relates to a NAND type flash memory or other semiconductor memory device having memory strings connected to bit lines and source lines via selection switches and to a signal processing system provided with such a semiconductor memory device, more particularly relates to an error correction processing technology of a semiconductor memory device.
2. Description of the Related Art
In a NAND type flash memory, a plurality of memory transistors are connected in series to form memory strings. Two memory strings share one bit contact and source line, whereby a higher integration is achieved.
In a general NAND type flash memory, an erase operation is performed by, for example, applying 0V to all word lines to which a selected memory string is connected, making all word lines to which unselected memory strings are connected floating states, and applying a high voltage (20V) to the substrate of the memory array. As a result, electrons are drained from the floating gates to the substrate for only the memory transistors of the selected memory string. As a result, the threshold voltages of the memory transistors shift to the negative direction and become, for example, −3V.
Further, data is written in units of so-called “pages” of several hundreds to several thousands bytes for memory transistors connected to the selected word line all together. Specifically, for example, a high voltage (for example, 18V) is applied to the selected word lines, 0V is applied to bit lines to which memory transistors into which data is to be written (0 data) are connected, and a high level voltage (for example 3.3V) is applied to bit lines to which memory transistors for which the writing is to be prohibited (1 data) are connected. As a result, electrons are injected into the floating gates for only the selected memory transistors into which the data is to be written. The threshold voltages of the selected memory transistors shift to the positive direction and become, for example, about 2V.
In such a NAND type flash memory, data is both written and erased by an FN (Fowler Nordheim) tunnel current, so there is the advantage that supply of an operation current from a booster circuit in a chip is relatively easy and operation with a single power supply is easy. Further, since the data is written into the memory transistors connected to the selected word lines all together in units of pages, this is superior to a NOR type flash memory in the point of the write speed.
In a nonvolatile semiconductor memory device for performing page write operations in units of word line sectors like the above mentioned NAND type flash memory, the data is written into all memory cells connected to the selected word line all together. However, the memory cells connected to the selected word line vary in size due to the production process, so differences occur in the write speed. Specifically, in a nonvolatile semiconductor memory device performing page write operations in units of word line sectors like a NAND type flash memory, a distribution arises in the time required for writing among memory cells.
Taking such variation as the write speed in account, from the viewpoint of keeping the distribution of the threshold voltage Vth at the time of the write operation narrow in a general NAND type flash memory, etc., the write operation is carried out through a verify operation. This write/verify operation is repeated until all memory cells finish being written by successively prohibiting the write operations from the memory cell finished being written for a so-called bit verify operation. In the case of a general memory cell, however, the time taken for programming is t0, but there will sometimes very rarely be memory cells which take an extremely long programming time of, for example, t1 (>t0) or more due to variation in the process. In such a case, the number of times of the above write/verify operation is set to a large number of, for example, 100 times or more for such a rare memory cell with such a slow write speed.
Further, the data is read into the NAND type flash memory by establishing the data stored in the memory cells through a sense amplifier and storing the data in a data register in units of random accessed pages, then serially transferring the page data to the outside in units of one or two bytes. Specifically, for example, a voltage of 0V is supplied to the selected word line and a voltage of about 4V is supplied to the unselected word lines. In the case of a NAND type flash memory, a plurality of memory cells is connected in series, therefore the read current of the memory cells is small in comparison with the NOR type flash memory, and thus the so-called “random access time” for establishing the data stored in the memory cells through the sense amplifier is long.
Further, in error correction of a nonvolatile semiconductor memory device, such as a NAND type flash memory, a redundant memory area is provided. A defective portion is found before shipment of the product and physically replaced by this redundant memory. The main type of error correction code (ECC) used is a hamming code, BCH code, or other code for error correction in units of bits.